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Our expression does not involve the solution of the differential equations characterizing the system as in [7] and is simple enough to be used during design and verification. Our noise amplitude bound could be considered to be analogous to the signal delay bounds in [8] which have been the foundation for many interconnect design algorithms. We have developed a router guided by our new measure and use our analysis results to show that the charge sharing model used in previous work on coupled noise-driven layout ([9], [10], [11]) is extremely pessimistic.

Upper and lower bounds on the coupled noise expression are determined along with upper and lower bounds for the right hand side of the inequality in Theorem 4. This allows quick and accurate identification of coupled noisecritical nets. In order to keep the number of vias required from becoming excessive, only two jogs per column for coupled noise reduction are allowed. Tradeoff exploration of jogs for coupled noise reduction is possible by modifying the jog insertion heuristic. Almost every stage of the greedy channel router can be modified to reflect coupled noise concerns.

Svensson, "Noise in digital dynamic CMOS circuits", IEEE Journal of Solid-State Circuits, June 1994, pp. 655-662. I. E. Butner, Gallium Arsenide Digital IC Design, McGraw-Hill, 1990, Ch. 5. R. J. Rymaszewski, Microelectronics Packaging Handbook, Van Nostrand Reinhold, 1989. [5] L. Gal, "On-chip crosstalk - the new signal integrity challenge", Proceedings of the Custom Integrated Circuits Conference, 1995, pp. 4. A. Katopis, "Delta-I noise specification for a high-performance computing machine", Proceedings of the IEEE, September 1985, pp.

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